A latchup is an inadvertent creation of a low-impedance path in an integrated circuit as a result of triggering a parasitic device in the integrated circuit. Latchup may happen anywhere in the integrated circuit where a parasitic structure (which is a structure that is inadvertently formed by placement of two or more devices in close proximity, such as a parasitic PNPN structure, which forms a silicon-controlled rectifier (SCR)) exists. A single event latchup (SEL) may be caused by a number of triggering factors, such as cosmic rays, spikes of voltage on an input or output terminal of the integrated circuit, other event. If an SEL occurs in the integrated circuit, excessive current may flow through the created low-impedance path, and the circuit in which the SEL has occurred may be destroyed by the excessive current. CMOS devices have inherent parasitic PNPN structures that are formed during fabrication of transistors in a semiconductor substrate. While technology is trending toward the development of smaller and higher performance integrated circuits, CMOS devices become more susceptible to SELs.
Testing for potential SEL sites is typically accomplished by scanning the circuit with neutron beams at an integrated repair operations center (IROC). At IROC, the circuit to be tested is placed under neutron beams and SELs are determined by counting the number of upsets that occurred in the entire integrated circuit. The testing only can indicate whether an SEL occurred, but cannot detect where the SEL occurred in the circuit, unless the circuit was functionally tested simultaneously under the neutron beam using a test program. In addition, the operator needs to know the layout of the circuit in order to find out the origin of the SEL. Moreover, the testing at IROC is costly, time consuming, requires waiting for one of the periods when the facility is available for such testing (about twice a year), and requires significant preparation with regard to boards, hardware, and programming.
Therefore, there is a need for better devices and methods that can test whether there is a potentiality that an SEL may occur in the circuit, and determine the potential origins of SELs in the circuits.